View EN25P05-75GIP_3825603.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 1 en25p05 rev. b, issue date: 2006 / 12 / 27 features ? single power supply operation - full voltage range: 2.7-3.6 volt ? 512 kbit serial flash - 512 k-bit/64 k-byte/256 pages - 256 bytes per programmable page ? high performance - 75mhz clock rate ? low power consumption - 5 ma typical active current - 1 a typical power down current ? uniform sector architecture: - two 32-kbyte sectors ? software and hardware write protection: - write protect all or portion of memory via software - enable/disable protection with wp# pin ? high performance program/erase speed - byte program time: 8s typical - page program time: 1.5ms typical - sector erase time: 500ms typical - chip erase time: 1 seconds typical ? minimum 100k endurance cycle ? package options - 8 pins sop 150mil body width - 8 contact vdfn - all pb-free packages are rohs compliant ? commercial and industrial temperature range general description the en25p05 is a 512 k-bit (64k-byte) serial flash memory, with advanced write protection mechanisms, accessed by a high speed spi-compatible bus. the memory can be programmed 1 to 256 bytes at a time, using the page program instruction. the en25p05 is designed to allow either single sector at a time or full chip erase operation. the en25p05 can be configured to protect part of the memory as the software protected mode. the device can sustain a minimum of 100k program/erase cycles on each sector. en25p05 512 kbit uniform sector , serial flash memory
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 2 en25p05 rev. b, issue date: 2006 / 12 / 27 figure.1 connection diagrams figure 2. block diagram 8 - lead sop 8 - contact vdfn
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 3 en25p05 rev. b, issue date: 2006 / 12 / 27 signal description serial data input (di) the spi serial data input (di) pin provides a means for instructions, addresses and data to be serially written to (shifted into) the device. data is latched on the rising edge of the serial clock (clk) input pin. serial data output (do) the spi serial data output (do) pin provides a means for data and status to be serially read from (shifted out of) the device. data is shifted out on the falling edge of the serial clock (clk) input pin. serial clock (clk) the spi serial clock input (clk) pin provides the timing for serial input and output operations. ("see spi mode") chip select (cs#) the spi chip select (cs#) pin enables and disables device operation. when cs# is high the device is deselected and the serial data output (do) pin is at high impedance. when deselected, the devices power consumption will be at standby levels unless an internal erase, program or status register cycle is in progress. when cs# is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. after power-up, cs# must transition from high to low before a new instruction will be accepted. hold (hold#) the hold pin allows the device to be paused while it is actively selected. when hold is brought low, while cs# is low, the do pi n will be at high impedance and si gnals on the di and clk pins will be ignored (don?t care). the hold function can be useful when multiple devices are sharing the same spi signals. write protect (wp#) the write protect (wp#) pin can be used to prevent the status register from being written. used in conjunction with the status register?s block protect (bp0, bp1) bits and status register protect (srp) bits, a portion or the entire memory array can be hardware protected. table 1. pin names symbol pin name clk serial clock input di serial data input do serial data output cs# chip enable wp# write protect hold# hold input vcc supply voltage (2.7-3.6v) vss ground
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 4 en25p05 rev. b, issue date: 2006 / 12 / 27 memory organization the memory is organized as: z 65,536 bytes z uniform sector architecture two 32-kbyte sectors z 256 pages (256 bytes each) each page can be individually programmed (bits are pr ogrammed from 1 to 0). the device is sector or bulk erasable but not page erasable. table 2. block sector architecture sector sector size (kbyte) address range 1 32 08000h ? 0ffffh 0 32 00000h ? 07fffh
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 5 en25p05 rev. b, issue date: 2006 / 12 / 27 operating features spi modes the en25p05 is accessed through an spi compatible bus consisting of four signals: serial clock (clk), chip select (cs#), serial data i nput (di) and serial data output (do). both spi bus operation modes 0 (0,0) and 3 (1,1) are supported. the primary difference between mode 0 and mode 3, as shown in figure 3, concerns the normal state of the sck signal when the spi bus master is in standby and data is not being transferred to the serial flash. for mode 0 th e sck signal is normally low. for mode 3 the sck signal is normally high. in either case data input on the di pin is sampled on the rising edge of the sck. data output on the do pin is clo cked out on the falling edge of sck. figure 3. spi modes page programming to program one data byte, two instructions are required: write enable (wren), which is one byte, and a page program (pp) sequence, which consists of four bytes plus data. this is followed by the internal program cycle (of duration tpp). to spread this overhead, the page program (pp) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. sector erase and bulk erase the page program (pp) instruction allows bits to be reset from 1 to 0. before this can be applied, the bytes of memory need to have been erased to all 1s (ffh). this can be achieved either a sector at a time, using the sector erase (se) instruction, or throughout the entire memory, using the bulk erase (be) instruction. this star ts an internal erase cycle (of duration tse or tbe). the erase instruction must be preceded by a write enable (wren) instruction. polling during a write, program or erase cycle a further improvement in the time to write status register (wrsr), program (pp) or erase (se or be) can be achieved by not waiting for the worst case de lay (tw, tpp, tse, or tbe). the write in progress (wip) bit is provided in the status re gister so that the application prog ram can monitor its value, polling it to establish when the previous write cycle, program cycle or erase cycle is complete. active power, stand-by power and deep power-down modes when chip select (cs#) is low, the device is enabled, and in the active power mode. when chip select (cs#) is high, the device is disabled, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). the device then goes in to the stand-by power mode. the device consumption drops to i cc1 . the deep power-down mode is entered when the specific instruction (the enter deep power-down mode (dp) instruction) is executed. the device consumption drops further to i cc2 . the device remains in this mode until another specific instruction (the release from deep power-down mode and read device id (rdi) instruction) is executed. all other instructions are ignored while the device is in the deep power-down mode. this can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent write, program or erase instructions.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 6 en25p05 rev. b, issue date: 2006 / 12 / 27 status register. the status register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. busy bit. the busy bit indicates whether the memory is bu sy with a write status register, program or erase cycle. wel bit. the write enable latch (wel) bit indicates the status of the internal write enable latch. bp1, bp0 bits. the block protect (bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase instructions. srp bit. the status register protect (srp) bit is operated in conjunction with the write protect (wp#) signal. the status register protect (srp) bit and write protect (wp#) signal allow the device to be put in the hardware protected mode. in this mode, the non-volatile bits of the status register (srp, bp1, bp0) become read-only bits. write protection applications that use non- volatile memory must take into consideration the po ssibility of noise and other adverse system conditions that may compromise data integrity. to address this concern the en25p05 provides the following data protection mechanisms: z power-on reset and an internal timer (t puw ) can provide protection against inadvertent changes while the power supply is outside the operating specification. z program, erase and write status register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. z all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit . th is bit is returned to its rese t state by the following events: ? power-up ? write disable (wrdi) instruction completion or write status register (wrsr) instruction completion or page program (pp) instruction completion or sector erase (se)instruction completion or bulk erase (be) instruction completion or z the block protect (bp1, bp0) bits allow part of the memory to be configured as read-only. this is the software protected mode (spm). z the write protect (wp#) signal allows the block pr otect (bp1, bp0) bits and status register protect (srp) bit to be protected. this is the hardware protected mode (hpm). z in addition to the low power consumption feature, the deep power-down mode offers extra software protection from inadvertent write, program and erase instructions, as all instructions are ignored except one particular instruction (the release from deep power-down instruction). table 3. protected area sizes sector organization memory content bp1 bit bp0 bit protected sectors addresses density(kb) portion 1 1 all ( sector 0 to 1) 000000h-00ffffh 64kb all sectors 1 0 0 1 pp(page program), and se(sector erase) is enabled without checking address. all sectors are protected against be(bulk erase). 0 0 none none none none hold function the hold (hold) signal is used to pause any serial communications with the devi ce without re setting the clocking sequence. howeve r, taking this signal low does not terminate any write status register, program or erase cycle that is currently in progress.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 7 en25p05 rev. b, issue date: 2006 / 12 / 27 to enter the hold condition, the device must be sele cted, with chip select (cs# ) low. the hold condition starts on the falling edge of the hold (hold) signal, provided that this coincides with serial clock (clk) being low (as shown in figure 4.). the hold condition ends on the rising edge of the hold (hold) signal, provided that this coincides with serial clock (clk) being low. if the falling edge does not coincide with serial cloc k (clk) being low, the hold condition starts after serial clock (clk) next goes low. similarly, if the ri sing edge does not coincide with serial clock (clk) being low, the hold condition ends after serial clock (clk) next goes low. (this is shown in figure 4.). during the hold condition, the serial data output (do) is high impedance, and serial data input (di) and serial clock (clk) are don?t care. normally, the device is kept selected, with chip select (cs#) driven low, for the whole duration of the hold condition. this is to ensure that the state of the internal logic remains unchanged from the moment of entering the hold condition. if chip select (cs#) goes high while the device is in the hold condition, this has the effect of resetting the internal logic of the device. to restart communication wi th the device, it is necessa ry to drive hold (hold) high, and then to drive chip select (cs#) low. this prevents the device from going back to the hold condition. figure 4. hold condition waveform instructions all instructions, addresses and data are shifted in and out of the device, most si gnificant bit first. serial data input (di) is sampled on the first rising edge of serial clock (clk) after chip select (cs#) is driven low. then, the one-byte instruction code must be sh ifted in to the device, mo st significant bit first, on serial data input (di), each bi t being latched on the rising edges of serial clock (clk). the instruction set is listed in table 4. every instruction sequence st arts with a one-byte instruction code. depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. chip select (cs#) must be driven high after the last bit of the instruction sequence has been shifted in. in the case of a read data bytes (read), read data bytes at higher speed (fast_read), read status register (rdsr) or release from deep power-down, and read device id (rdi) instruction, the shifted-in instruction sequence is followed by a data-out sequence. chip select (cs#) can be driven high after any bit of the data-out sequence is being shifted out. in the case of a page program (pp), sector erase (se), bulk erase (be), write status register (wrsr), write enable (wren), write disabl e (wrdi) or deep power-down (dp) instruction, chip select (cs#) must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. that is, chip select (cs#) must driven high when the number of clock pulses after chip select (cs#) being driven low is an ex act multiple of eight. all attempts to access the memory array during a write status regi ster cycle, program cycle or erase cycle are ignored, and the internal write status register cycle, prog ram cycle or erase cycle continues unaffected.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 8 en25p05 rev. b, issue date: 2006 / 12 / 27 table 4. instruction set instruction name byte 1 code byte 2 byte 3 byte 4 byte 5 byte 6 n-bytes write enable 06h write disable 04h read status register 05h (s7-s0) (1) continuous (2) write status register 01h s7-s0 read data 03h a23-a16 a15-a8 a7-a0 (d7-d0) (next byte) continuous fast read 0bh a23-a16 a15-a8 a7-a0 dummy (d7-d0) (next byte) continuous page program 02h a23-a16 a15-a8 a7-a0 d7-d0 (next byte) continuous sector erase d8h a23-a16 a15-a8 a7-a0 bulk erase c7h deep power-down b9h release from deep power-down, and read device id dummy dummy dummy (id7-id0) (4) release from deep power-down abh manufacturer/ device id 90h dummy dummy 00h (5) (m7-m0) (id7-id0) read identification 9fh (m7-m0) (id15-id8) (id7-id0) notes: 1. data bytes are shifted with most significant bit first. byte fields with data in parenthesis ?( )? indicate data being read from the device on the do pin. 2. the status register contents will repeat continuously until cs# terminate the instruction. 3. all sectors may use any address within the sector. 4. the device id will repeat continuously until cs# terminate the instruction. 5. the manufacturer id and device id bytes will repeat continuously until cs# terminate the instruction. 00h on byte 4 starts with mid and alternate with did, 01h at byte 4 starts did and alternate with mid. table 5. manufacturer and device identification op code (m7-m0) (id15-id0) (id7-id0) abh 5h 90h 1ch 5h 9fh 1ch 2010h
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 9 en25p05 rev. b, issue date: 2006 / 12 / 27 write enable (wren) (06h) the write enable (wren) instruction (figure 5) sets the write enable latch (wel) bit. the write enable latch (wel) bit must be set prior to every page program (pp), sector erase (se), bulk erase (be) and write status register (wrsr) instruction. the write enable (wren) instruction is entered by driv ing chip select (cs#) low, sending the instruction code, and then driving chip select (cs#) high. write disable (wrdi) (04h) the write disable instruction (figure 6) resets the wr ite enable latch (wel) bit in the status register to a 0. the write disable instruction is entered by driving chip select (cs#) low, shi fting the instruction code ?04h? into the di pin and then driving chip select (cs#) high. note that the wel bit is automatically reset after power-up and upon completion of the write status register, page program, sector erase, and bulk erase instructions.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 10 en25p05 rev. b, issue date: 2006 / 12 / 27 read status register (rdsr) (05h) the read status register (rdsr) instruction allows the status register to be read. the status register may be read at any time, even wh ile a program, erase or write stat us register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is al so possible to read the status register continuously, as shown in figure 7. table 6. status register bit locations srp 0 0 0 bp1 bp0 wel busy the status and control bits of th e status register are as follows: busy bit. the busy bit indicates whether the memory is busy with a write status register, program or erase cycle. when set to 1, such a cycle is in prog ress, when reset to 0 no su ch cycle is in progress. wel bit. the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write status register, program or erase instruction is accepted. bp1, bp0 bits. the block protect (bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase instructio ns. these bits are written with the write status register (wrsr) instruction. when one or both of the block protect (bp1, bp0) bits is set to 1, the relevant memory area (as defined in table 3.) becomes protected against page program (pp) and sector erase (se) instructions. the block protect (bp1, bp0) bits can be written provided that the hardware protected mode has not been set. the bulk erase (be) instruction is executed if, and only if, both block protect (bp1, bp0) bits are 0. reserved bit. status register bit locations 5 and 6 are reserved fo r future use. current devices will read 0 for these bit locations. it is recommended to mask out the reserved bit when testing the status register. doing this will ensure compatib ility with future devices. srp bit. the status register protect (srp) bit is operated in conjunction with the write protect (wp#) signal. the status register write protect (srp) bit an d write protect (wp#) signal allow the device to be put in the hardware protected mode (when the status register protect (srp) bit is set to 1, and write protect (wp#) is driven low). in this mode, the non-volatile bits of the status register (srp, bp1, bp0) become read-only bits and the write status register (wrsr) instruction is no longer accepted for execution. status register protect reserved bits block protect bits write enable latch busy
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 11 en25p05 rev. b, issue date: 2006 / 12 / 27 write status register (wrsr) (01h) the write status register (wrsr) instruction allows new values to be written to the status register. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch (wel). the write status register (wrsr) instruction is entered by driving chip select (cs#) low, followed by the instruction code and the data by te on serial data input (di). the instruction sequence is shown in figure 8.. the write status register (wrsr) instruction has no effect on s6, s5, s1 and s0 of the status register. s6 and s5 are always read as 0. chip select (cs#) must be driven high after the eighth bit of the data byte has been latched in. if not, the write status register (wrsr) instruction is not executed. as soon as chip select (cs#) is driven high, the self-timed write status register cycle (whose du ration is tw) is initiated. while t he write status register cycle is in progress, the status register may still be read to che ck the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch (wel) is reset. the write status register (wrsr) instruction allows the user to change the values of the block protect (bp1, bp0) bits, to define the size of the area that is to be treated as read-only, as defined in table 3.. the write status register (wrsr) instruction also a llows the user to set or reset the status register protect (srp) bit in accordance with the write prot ect (wp#) signal. the status register protect (srp) bit and write protect (wp#) signal allow the device to be put in the hardware protected mode (hpm). the write status register (wrsr) instruction is not executed once the hardware protected mode (hpm) is entered.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 12 en25p05 rev. b, issue date: 2006 / 12 / 27 read data bytes (read) (03h) the device is first selected by dr iving chip select (cs#) low. the in struction code for the read data bytes (read) instruction is followed by a 3-byte address (a23-a0), each bit being latched-in during the rising edge of serial clock (c lk). then the memory contents, at that address, is shifted out on serial data output (do), each bit being shifted out, at a maximum frequency f r , during the falling edge of serial clock (clk). the instruction sequence is shown in figure 9.. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes (read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes (read) instructio n is terminated by driving chip select (cs#) high. chip select (cs#) can be driven high at any time during data output. any read data bytes (read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. read data bytes at higher speed (fast_read) (0bh) the device is first selected by dr iving chip select (cs#) low. the in struction code for the read data bytes at higher speed (fast_read) instruction is followed by a 3-byte address (a23-a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (clk). then the memory contents, at that address, is shifted out on serial data output (do), each bit being shifted out, at a maximum frequency f r , during the falling edge of serial clock (clk). the instruction sequence is shown in figure 10.. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes at higher speed (fast_read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes at higher speed (fast_read) in struction is term inated by driving chip select (cs#) high. chip select (cs#) can be driven high at any time during data outpu t. any read data bytes at higher speed (fast_read) instructio n, while an erase, program or writ e cycle is in progress, is rejected without having any effects on the cycle that is in progress.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 13 en25p05 rev. b, issue date: 2006 / 12 / 27 page program (pp) (02h) the page program (pp) instruction allows bytes to be programmed in the memory. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the page program (pp) instruction is entered by dr iving chip select (cs#) low, followed by the in- struction code, three address bytes and at least one data byte on serial data input (di). if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (a7-a0) are all zero). chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 11. if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. chip select (cs#) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the page program (pp) instruction is not executed. as soon as chip select (cs#) is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page program cycle, and is 0 when it is co mpleted. at some unspecified time before the cycle is completed, the write enable latch (w el) bit is reset. a page program (pp) instruction applied to a page which is protected by the block protect (bp1, bp0) bits (see table 3.a and table 3.b) is not executed.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 14 en25p05 rev. b, issue date: 2006 / 12 / 27 sector erase (se) (d8h) the sector erase (se) instruction sets to 1 (ffh) all bits inside the chosen sector. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the sector erase (se) instruction is entered by dr iving chip select (cs#) low, followed by the in- struction code, and three address bytes on serial data input (di). any address inside the sector (see table 2.a and table 2.b) is a valid address for the sector erase (se) instruction. chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 12.. chip select (cs#) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the sector erase (se) instruction is not executed. as soon as chip select (cs#) is driven high, the self-timed sector erase cycle (whose duration is t se ) is initiated. while the sector er ase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. at some unspecifie d time before the cycle is completed, the write enable latch (wel) bit is reset. a sector erase (se) instruction applied to a page which is protected by the block protect (bp1, bp0) bits (see table 3.a and table 3.b) is not executed.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 15 en25p05 rev. b, issue date: 2006 / 12 / 27 bulk erase (be) (c7h) the bulk erase (be) instruction sets all bits to 1 (ffh). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the bulk erase (be) instruction is entered by drivin g chip select (cs#) low, followed by the instructio n code on serial data input (di). chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 13.. chip select (cs#) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the bulk erase instruction is not executed. as soon as chip select (cs#) is driven high, the self-timed bulk erase cycl e (whose duration is t be ) is initiated. while the bu lk erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed bulk erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. the bulk erase (be) instruction is executed only if all block protect (bp1, bp0) bits are 0. the bulk erase (be) instruction is ignored if one, or more, sectors are protected.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 16 en25p05 rev. b, issue date: 2006 / 12 / 27 deep power-down (dp) (b9h) executing the deep power-down (dp) instruction is the only way to put the device in the lowest con- sumption mode (the deep power-down mode). it c an also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all write, program and erase instructions. driving chip select (cs#) high deselects the device, and puts the device in the standby mode (if there is no internal cycle currently in progress). but this mode is not the deep power-down mode. the deep power-down mode can only be entered by executing the deep power-down (dp) instruction, to reduce the standby current (from i cc1 to i cc2 , as specified in table 8.). once the device has entered the deep power-down mode, all instructions are ignored except the release from deep power-down and read device id (rdi) inst ruction. this releases the device from this mode. the release from deep power-down and read device id (rdi) instruction also allows the device id of the device to be output on serial data output (do). the deep power-down mode automatically stops at power-down, and the device always powers-up in the standby mode. the deep power-down (dp) instructio n is entered by driving chip select (cs#) low, followed by the instruction code on serial data input (di). chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 14..chip se lect (cs#) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the deep power-down (dp) instruction is not executed. as soon as chip select (cs#) is driven high, it requires a delay of t dp before the supply current is reduced to i cc2 and the deep power-down mode is entered. any deep power-down (dp) instruction, while an erase, program or write cycle is in progress, is rejected without having any e ffects on the cycle that is in progress. release from deep power-down and read device id (rdi) once the device has entered the deep power-down mode, all instructions are ignored except the release from deep power-down and read device id (rdi) instruction. executing this instruction takes the device out of the deep power-down mode. please note that this is not the same as, or even a subset of, the jedec 16-bit electronic signature that is read by the read identifier (rdid) instruction. the old-style electronic signature is supported for reasons of backward compat ibility, only, and sh ould not be used for new de signs. new des igns should, instead, make use of the jedec 16-bit electronic signature, and the read identifier (rdid) instruction. when used only to release the device from the power-down state, the instruction is issued by driving the cs# pin low, shifting the instruction code ?abh? and driving cs# high as shown in figure 15. after the time duration of t res1 (see ac characteristics) the device will resume normal operation and other instructions will be accepted. the cs # pin must remain high during the t res1 time duration. when used only to obtain the device id while not in the power-down state, the instruction is initiated by driving the cs# pin low and shifting the instruction code ?abh? followed by 3-dummy bytes. the device id bits are then shifted out on the falling edge of clk with most signif icant bit (msb) first as shown in figure
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 17 en25p05 rev. b, issue date: 2006 / 12 / 27 16. the device id value for the en25p05 are listed in table 5. the device id can be read continuously. the instruction is comp leted by driving cs# high. when chip select (cs#) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power-down mode, the tran sition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transiti on to the standby power mode is delayed by t res2 , and chip select (cs#) must remain high for at least t res2 (max), as specified in table 10. once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. except while an erase, program or write status register cycle is in progress, the release from deep power-down and read device id (rdi) instruction always provides access to the 8bit device id of the device, and can be applied even if the deep power-down mode has not been entered. any release from deep power-down and read device id (rdi) instruction while an erase, program or write status register cycle is in progress, is not de coded, and has no effect on the cycle that is in progress.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 18 en25p05 rev. b, issue date: 2006 / 12 / 27 read manufacturer / device id (90h) the read manufacturer/device id instruction is an alternative to the release from power-down / device id instruction that provides both the jedec assign ed manufacturer id and the specific device id. the read manufacturer/device id instruction is very similar to the release from power-down / device id instruction. the instruction is initiated by driving th e cs# pin low and shifting the instruction code ?90h? followed by a 24-bit address (a23-a0) of 000000h. after which, the manufacturer id for eon (1ch) and the device id are shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 17. the device id values for the en25p05 are lis ted in table 5. if the 24-b it address is initially set to 000001h the device id will be read first
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 19 en25p05 rev. b, issue date: 2006 / 12 / 27 read identification (rdid)(9fh) the read identification (rdid) instru ction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. the device identif ication indicates the memory type in the first byte , and the memory capacity of the device in the second byte . any read identification (rdid) instru ction while an erase or program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the read identification (rdid) instruction should not be issued while the device is in deep power down mode. the device is first selected by driving chip select low. then, the 8-bit instruction code for the instruction is shifted in. this is followed by th e 24-bit device identification, stored in the memory, being shifted out on serial data output , each bit bein g shifted out during the falling edge of serial clock . the instruction sequence is shown in figure 18. the read identification (rdid) instruction is terminated by driving chip select high at any time during data output. when chip select is driven high, the device is put in the standby power mode. once in the standby power mode, the device waits to be selected, so that it can receive, decode and execute instructions. figure 18. read identification (rdid)
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 20 en25p05 rev. b, issue date: 2006 / 12 / 27 power-up timing figure 19. power-up timing table 7. power-up timing and write inhibit threshold symbol parameter min. max. unit tvsl (1) vcc(min) to cs# low 10 s tpuw (1) time delay to write instruction 1 10 ms vwi (1) write inhibit voltage 1 2 v note: 1.the parameters are characterized only. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0).
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 21 en25p05 rev. b, issue date: 2006 / 12 / 27 table 8. dc characteristics (t a = 0c to 70c or - 40c to 85c; v cc = 2.7-3.6v) symbol parameter test conditions min. max. unit i li input leakage current 2 a i lo output leakage current 2 a i cc1 standby current cs# = v cc , v in = v ss or v cc 10 a i cc2 deep power-down current cs# = v cc , v in = v ss or v cc 10 a clk = 0.1 v cc / 0.9 v cc at 75mhz, q = open 20 ma clk = 0.1 v cc / 0.9 v cc at 50mhz, q = open 15 ma i cc3 operating current (read) clk = 0.1 v cc / 0.9 v cc at 33mhz, q = open 12 ma i cc4 operating current (pp) cs# = v cc 15 ma i cc5 operating current (wrsr) cs# = v cc 15 ma i cc6 operating current (se) cs# = v cc 15 ma i cc7 operating current (be) cs# = v cc 15 ma v il input low voltage ? 0.5 0.3 v cc v v ih input high voltage 0.7v cc v cc +0.4 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = ?100 a v cc -0.2 v table 9. ac measurement conditions symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltages 0.2 v cc to 0.8 v cc v input timing reference voltages 0.3 v cc to 0.7 v cc v output timing reference voltages v cc / 2 v figure 20. ac measurement i/o waveform
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 22 en25p05 rev. b, issue date: 2006 / 12 / 27 table 10. 75mhz ac characteristics (t a = 0c to 70c or - 40c to 85c; v cc = 2.7-3.6v) symbol alt parameter min typ max unit f r f c serial clock frequency for: fast_read, pp, se, be, dp, res, wren, wrdi, rdsr, wrsr d.c. 75 mhz f r serial clock frequency read instruction d.c. 50 mhz t clh 1 serial clock high time 6 ns t cll 1 serial clock low time 6 ns t clch 2 serial clock rise time (slew rate) 0.1 v / ns t chcl 2 serial clock fall time (slew rate) 0.1 v / ns t slch t css cs# active setup time 5 ns t chsh cs# active hold time 5 ns t shch cs# not active setup time 5 ns t chsl cs# not active hold time 5 ns t shsl t csh cs# high time 100 ns t shqz 2 t dis output disable time 6 ns t clqx t ho output hold time 0 ns t dvch t dsu data in setup time 5 ns t chdx t dh data in hold time 5 ns t hlch hold# low setup time ( relative to sck ) 5 ns t hhch hold# high setup time ( relative to sck ) 5 ns t chhh hold# low hold time ( relative to sck ) 5 ns t chhl hold# high hold time ( relative to sck ) 5 ns t hlqz 2 t hz hold# low to high-z output 6 ns t hhqz 2 t lz hold# high to low-z output 6 ns t clqv t v output valid from sck 6 ns t whsl 3 write protect setup time before cs# low 20 ns t shwl 3 write protect hold time after cs# high 100 ns t dp 2 cs# high to deep power-down mode 3 s t res1 2 cs# high to standby mode without electronic signature read 3 s t res2 2 cs# high to standby mode with electronic signature read 1.8 s t w write status register cycle time 10 15 ms t pp page programming time 1.5 5 ms t se sector erase time 32kb sectors 0.5 1 s t be bulk erase time 1 2 s note: 1. t s ckh + t s ckl must be greater than or equal to 1/ f clk 2. value guaranteed by characterization, not 100% tested in production. 3. only applicable as a constraint for a write status register instruction when status register protect bit is set at 1.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 23 en25p05 rev. b, issue date: 2006 / 12 / 27 table 11. 50mhz ac characteristics (t a = 0c to 70c or - 40c to 85c; v cc = 2.7-3.6v) symbol alt parameter min typ max unit f r f c serial clock frequency for: fast_read, pp, se, be, dp, res, wren, wrdi, rdsr, wrsr d.c. 50 mhz f r serial clock frequency read instruction d.c. 33 mhz t clh 1 serial clock high time 9 ns t cll 1 serial clock low time 9 ns t clch 2 serial clock rise time (slew rate) 0.1 v / ns t chcl 2 serial clock fall time (slew rate) 0.1 v / ns t slch t css cs# active setup time 5 ns t chsh cs# active hold time 5 ns t shch cs# not active setup time 5 ns t chsl cs# not active hold time 5 ns t shsl t csh cs# high time 100 ns t shqz 2 t dis output disable time 9 ns t clqx t ho output hold time 0 ns t dvch t dsu data in setup time 5 ns t chdx t dh data in hold time 5 ns t hlch hold# low setup time ( relative to sck ) 5 ns t hhch hold# high setup time ( relative to sck ) 5 ns t chhh hold# low hold time ( relative to sck ) 5 ns t chhl hold# high hold time ( relative to sck ) 5 ns t hlqz 2 t hz hold# low to high-z output 9 ns t hhqz 2 t lz hold# high to low-z output 9 ns t clqv t v output valid from sck 9 ns t whsl 3 write protect setup time before cs# low 20 ns t shwl 3 write protect hold time after cs# high 100 ns t dp 2 cs# high to deep power-down mode 3 s t res1 2 cs# high to standby mode without electronic signature read 3 s t res2 2 cs# high to standby mode with electronic signature read 1.8 s t w write status register cycle time 10 15 ms t pp page programming time 1.5 5 ms t se sector erase time 32kb sectors 0.5 1 s t be bulk erase time 1 2 s note: 1. t s ckh + t s ckl must be greater than or equal to 1/ f clk 2. value guaranteed by characterization, not 100% tested in production. 3. only applicable as a constraint for a write status register instruction when status register protect bit is set at 1.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 24 en25p05 rev. b, issue date: 2006 / 12 / 27 figure 21. serial output timing figure 22. input timing figure 23. hold timing
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 25 en25p05 rev. b, issue date: 2006 / 12 / 27 absolute maximum ratings stresses above the values so mentioned above may cause permanent damage to the device. these values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. exposure of the device to th e maximum rating values for extended periods of time may adversely affect th e device reliability. parameter value unit storage temperature -65 to +125 c plastic packages -65 to +125 c output short circuit current 1 200 ma input and output voltage (with respect to ground) 2 -0.5 to +4.0 v vcc -0.5 to +4.0 v notes: 1. no more than one output shorted at a time. duration of the short circuit should not be greater than one second. 2. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, inputs may undershoot v ss to ?1.0v for periods of up to 50ns and to ?2.0 v for periods of up to 20ns. see figure below. maximum dc voltage on output and i/o pins is v cc + 0.5 v. during voltage transitions, outputs may overshoot to v cc + 1.5 v for periods up to 20ns. see figure below. recommended operating ranges 1 parameter value unit ambient operating temperature commercial devices industrial devices 0 to 70 -40 to 85 c regulated: 3.0 to 3.6 operating supply voltage vcc full: 2.7 to 3.6 v notes: 1. recommended operating ranges define those limits between which the functionality of the device is guaranteed. vcc +1.5v maximum negative overshoot waveform maximum positive overshoot waveform
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 26 en25p05 rev. b, issue date: 2006 / 12 / 27 table 12. data retention and endurance parameter description test conditions min unit 150c 10 years minimum pattern data retention time 125c 20 years erase/program endurance -40 to 85 c 100k cycles table 13. latch up characteristics parameter description min max input voltage with respect to v ss on all pins except i/o pins (including a9, reset and oe#) -1.0 v 12.0 v input voltage with respect to v ss on all i/o pins -1.0 v vcc + 1.0 v vcc current -100 ma 100 ma note : these are latch up characteristics and the device should never be put under these conditions. refer to absolute maximum ratings for the actual operating limits. table 14. capacitance ( v cc = 2.7-3.6v) parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 pf c out output capacitance v out = 0 8 pf note : sampled only, not 100% tested, at t a = 25c and a frequency of 20mhz.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 27 en25p05 rev. b, issue date: 2006 / 12 / 27 package mechanical figure 24. sop 150 mil
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 28 en25p05 rev. b, issue date: 2006 / 12 / 27 figure 25. vdfn8( 5x6mm ) min. nor max a 0.76 0.80 0.84 a1 0.00 0.02 0.04 a2 - - - 0.20 - - - d 5.90 6.00 6.10 e 4.90 5.00 5.10 d2 4.18 4.23 4.28 e2 3.95 4.00 4.05 e - - - 1.27 - - - b 0.35 0.40 0.45 l 0.55 0.60 0.65 note : 1. co p lanarit y : 0.1 mm symbol dimension in mm
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 29 en25p05 rev. b, issue date: 2006 / 12 / 27 ordering information en25p05 - 50 g c p packaging content (blank) = conventional p = rohs compliant temperature range c = commercial (0 c to +70 c) i = industrial (-40 c to +85 c) package g = 8-pin 150mil sop v = 8-pin vdfn speed 75 = 75 mhz 50 = 50 mhz base part number en = eon silicon solution inc. 25p = 3v serial uniform-sector flash 05 = 512 kbit (64k x 8)
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 30 en25p05 rev. b, issue date: 2006 / 12 / 27 revisions list revision no description date a initial release 2006/04/10 b 1. change clock rate from 50mhz to 75mhz, page program time 1.4 ms typical to 1.5 ms typical in page 1 2. change table 8 dc characteristics in page 21 (1) add i cc3 for 75mhz 3. change table 10 to 75mhz ac characteristics in page 22 (1) change f r from 50 to 75mhz (2) change f r from 33 to 50mhz (3) change t clh from 9ns to 6ns (4) change t cll from 9ns to 6ns (5) change t shqz from 9ns to 6ns (6) change t hlqz from 9ns to 6ns (7) change t hhqz from 9ns to 6ns (8) change t clqv from 9ns to 6ns (9) change page program time 1.4ms typical to 1.5ms 4. add table 11: 50mhz ac characteristics in page 23 (1) change page program time 1.4ms typical to 1.5ms 5. add 75mhz option in ordering information in page 29 2006/12/27

▲Up To Search▲

Price & Availability of EN25P05-75GIP

	To Download EN25P05-75GIP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .